Card image cap
Academic Qualification:


Degree Institute Year Board/University Percentage/CGPA Remarks
AISSE
(Class 10)
Kendriya Vidyalaya
Jorhat Assam
1995 CBSE 83.2 -
AISSCE
(Class 12)
Kendriya Vidyalaya
Jorhat Assam
1997 CBSE 80.2 -
B.E
(Dept. of CSE)
REC Durgapur 2001 Burdwan 79.7(1st Hons) 3rd in the University
MS(by Research) IIT Kharagpur
(Dept. of EE)
2004 - 10.0/10.0 Institute Highest CGPA of the year 2003-04
PhD IIT Kharagpur
(Dept. of CSE)
2008 - - -
Experiences

Job Experience:

July 2001-December 2001:
Development of Algorithms and Software for "Economic Generation Scheduling" for CESC Kolkata (a consultancy project under taken by SRIC, IIT Kharagpur)

January 2002-June 2008:
Research Consultant for Advanced VLSI Design Laboratory (Testing), IIT Kharagpur

May 2005--May 2006:
Research Consultant for a consultancy project undertaken by IIT Kharagpur and National Semiconductor Corp. USA on "Development of Template based CAD tools for Placement and Routing of Test Chips (TRET)"

June 2008-November 2008 :
Senior Lecturer, Department of CSE IIT Guwahati

November 2008 - February 2014:
Asst. professor, Department of CSE IIT Guwahati

March 2014-till date:
Asso. professor, Department of CSE IIT Guwahati

June 2018-till date:
Visiting Asso. professor, Department of EECS, IIT Bhilai





Courses taught
Serial No. Course Name UG/PG No. of Times Taughts
1 Theoretical Foundation of Computer System PG 2
2 CAD for VLSI PG+UG 2
3 Systems Programming Lab. UG 8
4 Systems Software Lab. UG 8
5 VLSI Design, Test and Verification UG+PG 3
6 Compilers UG 2
7 Compilers Lab. UG 2
8 Digital Logic and Computer Architecture Minor UG (Minor) 1
9 Computer Organization and Architecture UG 4
10 Digital Design UG 4



ICT based Teaching

1: NPTEL web course "VLSI Design Verification and Test"

2: NPTEL video course "Design Verification and Test of Digital VLSI Circuits"

3: Pedagogical Methods "Computer Organization and Architecture"

4: MOOCS course "VLSI Design Verification and Test" (2016)

5: MOOCS course "Computer Organization and Architecture: A Pedagogical Aspect" (2018)

6: MOOCS course "Optimization Techniques for Digital VLSI Design" (2018)

7: MOOCS course "Embedded Systems--Design Verification and Test" (2018)



Projects:

Academic Projects:

1. Algorithms and Software for solving Linearly Separable and Inseparable Problems of Pattern Classification
( Final Year Project for the Degree: Bachelor of Engineering ).

2. Algorithms and CAD tools and Design of Digital VLSI ICs for On-Line Monitoring of Digital VLSI Circuits
(Project for the Degree: MS by Research )
The CAD tool has been incorporated in the test flow used in Advanced VLSI Design Laboratory, IIT Kharagpur.

3. Impact of Fairness in Failure Detection and Diagnosis of Discrete Event Systems and application to VLSI Circuits
(Project for the Degree: PhD)


Sponsored and Consultancy Projects:

1. Title: Failure Detection and Diagnosis of Fair Distributed Discrete Event Systems and Its application to VLSI Circuits and Networks.
Sponsor: IIT Guwahati
Budget: 2.8 Lakhs
Duration: 2009-2010
Role: Principal Investigator

2. Title: Design, Development and Verification of Network Specific Intrusion Detection System using Failure Detection and Diagnosis of Discrete Event Systems.
Sponsor: DIT, New Delhi
Budget: 111.78 Lakhs
Duration: 2009-2011
Role: Co-Principal Investigator

3. Title: Remote Triggered Digital System Laboratory under Remote Triggered Lab.
Sponsor: MHRD, New Delhi
Budget: 49 Lakhs
Duration: 2011-2017
Role: Chief Investigator

4. Title: Development of Framework for Logging and Analysis of Network Traffic to secure IT infrastructure.
Sponsor: MCIT at Manipur University, CS dept. at Guwahati University, IT dept. at Assam University
Budget: 15 Lakhs
Duration: 2009-14
Role: Chief Investigator

5. Title: On line Testing of Complex VLSI Circuits using Failure Detection and Diagnosis Theory of Discrete Event Systems.
Sponsor: DIT, New Delhi
Budget: 124 Lakhs
Duration: 2013-17
Role: Chief Investigator

6. Title: Virtual Lab. Integration (Institute Coordinator IIT Guwahati)
Sponsor: MHRD, New Delhi
Budget: 247 Lakhs
Duration: 2014-
Role: Chief Investigator

7. Title: Information Security Research and Development Centre (ISRDC) under Information Security Education and Awareness (ISEA) Project (Phase-II)
Sponsor: Department of Electronics and Information Technology, Govt. of India
Budget: 344 Lakhs
Duration: 2015-20
Role: Co-Chief Investigator

8. Title: A Software Tool for the Planning and Design of Smart Micro Power Grids
Sponsor: IMPacting Research INnovation and Technology (IMPRINT), MHRD, Govt. of India
Budget: 202Lakhs
Duration: 2017-2019
Role: Co-Investigator

9. Title: Virtual Labs Phase-III
Sponsor: NMICTE under MHRD, Govt. of India
Budget: 15 Crores (total for all the consortium members)
Duration: 2018-2020
Role: National Lab Development Coordinator for Electrical Engineering

10. Title: Formal Methods for Modeling and verification of Intrusion Detection system in wireless Networks
Sponsor: Interdisciplinary Cyber Physical Systems (ICPS) Programme, (DST), Govt. of India, New Delhi
Budget: 34 Lakhs
Duration: (Technically approved subject to financial approval)
Role: Principal Investigator

11. Title: Game Theory Based Intrusion Detection System (IDS) for Cyber Physical System
Sponsor: Interdisciplinary Cyber Physical Systems (ICPS) Programme, (DST), Govt. of India, New Delhi
Budget: 39 Lakhs
Duration: (Technically approved subject to financial approval)
Role: Co-Investigator



PhD students

Serial No. Name Thesis Area Duration Co-Guide
1 Neminath Hubballi (now Asst. prof. at IIT Indore) Design of Network Intrusion Detection Systems:An Effective Alarm Generation Perspective 2008-2012 Prof. S Nandi
2 Ferdous A. Barbhuiya (now Asst. prof. at IIIT Guwahati) Design and Development of Intrusion Detection System: A Discrete Event System Approach 2009-2013 Prof. S Nandi
3 Amrita Bose Paul Intrusion Detection Systems for Wireless Mesh Networks 2009-2018 (Submitted) Prof. S Nandi
4 Mousum Handique VLSI Testing 2011- Dr. J.K. Deka
5 Pradeep Kumar Biswal (now Asst. prof. at IIIT Bhagalpur) Decision Diagrams Based On-line Testing of Digital VLSI Circuits 2012-2017 -
6 Mayank Agarwal (now Post. doc fellow in Israel University) Intrusion Detection System for Attacks in Wi-Fi Networks: A Discrete Event System Approach 2012-2017 Prof. S Nandi
7 Basant Subba On improving the effiency of intrusion detection systems using game theoretic approaches 2014-2018 Dr. S. Karmakar
8 Biswajit Bhowmik Performance-Aware Test-Time Optimization Schemes of Analysis of Logic Level Faults in Channels of On-Chip Networks 2014-2017 Dr. J.K. Deka
9 Piyoosh P Discrete Event Systems and Embedded Systems 2014- Dr. A Sarkar
10 Rajesh Devaraj Discrete Event System Approaches for RT Scheduler Design for Safety-critical Systems 2014-2018 (submitted) Dr. A Sarkar
11 Sisir Kumar Jena VLSI Testing 2015- Dr. J.K. Deka
12 Nanu Alan Kachari Virtual Labs. 2015- Dr. J.K. Deka
13 Pradeep Kumar Sharma Discrete Event Systems and High Level VLSI Testing 2014- Dr. J.K. Deka
14 Vasudevan M.S Processor Testing 2014- Dr. A. Sahu
15 Surajit Das Discrete Event Systems and High Level VLSI Testing 2014- Dr. C. Karfa




MTech students

Serial No. Name Thesis Area Duration Co-Guide
1 Rachuri Sreedhar False Alarm Reduction in SNORT Using Network Vulnerability Information 2007-09
2 Vikrant Kumar Singh Anomaly Detection through Clustering 2008-10 Prof. S. Nandi
3 Kushagra Misra FDES Application to On-line Testing of Asynchronous Circuits 2008-10 Dr. Hemangee K. Kapoor
4 Santosh Kumar Network Anomaly Detection using One-Class small Hypersphere Support Vector Machine 2008-10 Prof. S. Nandi
5 Sapna Kushwaha Detection of Kernel Level Root Kits using Loadable Kernel Modules 2008-10 Prof. S. Nandi
6 Rittesh Ratti Active Detection Mechanism for attacks in Autonomous Systems 2008-10 Prof. S. Nandi
7 Roopa S Active Detection Mechanism for attacks in Autonomous Systems 2008-10 Prof. S. Nandi
8 Dhrubajyoti Pathak An Intrusion Detection System for Kaminsky DNS Cache Poisoning 2008-10
9 Vivek S Ramteke Implementing VLAN Attacks and its Detection 2009-11 Prof. S. Nandi
10 Vaibhav Gupta Detection and Mitigation of Induced Low Rate TCP-targeted attack 2009-11
11 Shambho Haridas Pol Efficient ON-Line Tester for Digital VLSI Circuit 2009-11
12 Prithu Banerjee IDS for ICMP Network Attacks using Failure Diagnosis and Detection Theory of DES 2010-12 Prof. S. Nandi
13 Dasari Srinivas Online Testing of Digital VLSI circuits for Bridging Faults 2010-12
14 Mahasweta Mitra IDS for ARP Spoofing and NDP attacks using LTL based Discrete Event System Framework 2010-12 Prof. S. Nandi
15 Ashish Bhandari DES Based IDS for Throughput Degradation Attack on TCP 2010-12 Prof. S. Nandi
16 Ripunjoy Sonowal Specification Based Intrusion Detection System for SHORT-AODV 2010-12
17 Manab Mohan Borah Attack analysis on AODV with SHORT in Ad-Hoc Wireless Networks 2010-13
18 Leuva Pratikkumar Khushalbhai Hybrid System Approach to Online Fault Detection in Power Converter Circuit (Case Study : DC DC Boost Converter) 2011-13
19 Argha Sen A Discrete Event System Approach To Fault-Tolerant Real-Time Multiprocessor Systems 2011-13
20 Prabal Kumar Ghosh Discrete Event System Approach to Evil Twin Attack Detection 2011-13
21 Koushik Konar Online Testing of Digital Circuit Case Study at Comparator 2012-14
22 Kamaljeet Chauhan Real Time Scheduling strategies with incomplete information using Discrete Event System(DES) 2012-14
23 Piyoosh P Discrete Event System (DES) Approach to Fault Tolerance in Real Time System on Homogeneous and Heterogeneous Multiprocessor Platform 2012-14
24 Eyerusalem Dagnew Gebru Online Test for Reversible Circuit 2013-15
25 Berhe Gebrezghiabher Wekelle Online testing of reversible circuits using M-Out-of-N checker 2013-15
26 Mukesh Verma Handling Security Issue in EEOLSR Using Static Bayesian Game Approach 2013-15
27 LT. COL. Mandeep Singh Rai Detection and Mitigation of Identity Spoofing Attacks and Delba Attack in 802.11e Wireless Networks 2014-16
28 Jainendra Kumar Energy Efficient Migration Aware Proportional Fair Scheduling on Multiprocessor 2015-17
29 Sandeep Kumar Detection of Hidden Malicious Logic in Hardware Design Using Functional Analysis 2015-17
30 Partha Pritam Mahanta A Control Path Based Resource Evaluation Strategy for Malware Detection in Embedded Systems 2015-17
31 AJINKYA SANJAY MANKAR NOC Testing and Verification 2016-18
32 PAVAN GANESH JEEREDDY NOC Testing and Verification 2016-18








Publications:

Publications (International Journal)   :

1.    S Biswas, S Mukhopadhyay, A Patra, "A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation", Journal of Electronic Testing: Theory and Applications, Springer, Vol. 21, 2005, pp: 503-538, Impact factor 0.647.

2.    S Biswas, Dipankar Sarkar, Prodip Bhowal and Siddhartha Mukhopadhyay "Diagnosis of Delay-Deadline Failures in Real Time Discrete Event Models", Proc. of ISA Transactions, Elsevier, Vol. 46, Issue 4, pp: 569-582, 2007,Impact Factor: 3.394.

3.    S Biswas, D Sarkar, S Mukhopadhyay and A Patra, "Diagnosability Analysis of Discrete Time Hybrid Systems", Asian Journal of Control, Wiley, Vol. 10 Issue 6, pp: 651-665, 2008,Impact Factor: 1.421.

4.    S Biswas, S Mukhopadhyay, A Patra, D Sarkar, "Methodology for low-power design on on-line testers for digital VLSI circuits", International Journal of Electronics, Francis and Taylor, Vol. 95 No. 8, pp: 785-797, 2008,Impact Factor 0.729.

5.    S Biswas, Siddhartha Mukhopadhyay, Amit Patra, D Sarkar, "An unified methodology for on-line testing of delay and stuck-at faults in digital VLSI circuits", Journal of circuits, systems and computers, World Scientific Press, Vol. 17 Issue 6, pp: 1069-1089, 2008.

6.    S Biswas, D Sarkar, Siddhartha Mukhopadhyay, Amit Patra "Fairness of transitions in diagnosability analysis of discrete event systems", Journal of discrete event dynamic systems: theory and applications, Vol. 20, No. 3, September 2010, pp 349-376, Springer,Impact Factor 1.660.

7.    S Biswas, D Sarkar, Siddhartha Mukhopadhyay, "Diagnosability of Delay-Deadline Failures in Fair Real Time Discrete Event Models", International Journal of Systems Science, Vol. 41, No 7, July 2010, pp 763-782, Taylor and Francis
Impact factor 2.285.

8.    Neminath Hubballi, Santosh Biswas, Rupa S, Ritesh Ratti,Sukumar Nandi, ``Disrete Event Systems Approach to LAN Attack Detection", ISA Transactions, Vol 50, No1, Jan 2011, pp 119-130, Elsevier, Impact Factor: 3.394.

9.    N. Hubballi, S. Biswas, S. Nandi, "Network Specific False Alarm Minimization", Journal of Security and Communication Networks, Vol. 4, No. 11, pp 1339-1349, 2011, Wiley,Impact Factor: 1.067.

10.    Ferdous A Barbhuiya, Santosh Biswas, and Sukumar Nandi, " An active host-based intrusion detection system forARP-related attacks and its verification", International Journal of Network Security & Its Applications (IJNSA), Vol.3, No.3, May 2011, page 163-180, AIRCC Press (Adapted from Conference paper ---F.A. Barbhuiya, S Roopa, R Ratti, Neminath H, S Biswas, S Nandi, A Sur and V Ramachandra, "An Active Host-based Detection Mechanism for ARP-related Attacks", International Conference on Network & Communications Security (Netcom 2010), Chennai, India, pp- 432-443 (Springer),Impact factor 0.62.

11.    Santosh Biswas, "Diagnosability of Discrete Event System for Temporary Failures", Computers and Electrical Engineering, Vol. 38, No. 6, pp 1534-1549, 2012, Elsevier,Impact Factor: 1.570.

12.    N. Hubballi, S. Biswas, S. Nandi, "Towards Reducing False Alarms in Network Intrusion Detection Systems with Data Summarization Technique", Journal of Security and Communication Networks, Vol. 6, No. 3, pp 275-285, Wiley 2013,Impact Factor: 1.067.

13.    R Bhattacharya, S Biswas, S Mukhopadhyay, "FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits: A Case Study of DC-DC Buck Converter", Measurement, Vol. 45, No. 8., pp. 1997-2020, Elsevier, 2012,Impact Factor: 2.359.

14.    S. Chakraborty, F. A Barbhuiya, A. Rai, A. Sur, S. Biswas and S. Nandi, " Topology Adaptive Computation of Distributed IDS Set for Detecting Attacks on STP", Journal of Information Assurance and Security, Vol. 7, No. 5., pp. 284-295, 2012.

15.    A B Paul, S Konwar, S Nandi and S Biswas, "Trusted M-OLSR for Secure Routing in Wireless Mesh Networks", Journal of Information Assurance and Security, Vol. 8, No. 1, pp. 17-32, 2013.

16.    F.A. Barbhuiya, G Bansal, N Kumar, S. Biswas and S. Nandi, "Detection of Neighbor Discovery Protocol Based Attacks in IPv6 Network (SPECIAL ISSUE for SIN 2011)", Issue 3-4, Springer, Page 91-113, May 2013

17.    M. Mitra, P. Banerjee, F. A. Barbhuiya, S. Biswas and S. Nandi, "IDS for ARP Spoofing using LTL based Discrete Event System Framework (Special issue for SIN 2011)", Issue 3-4, Networking Science", Springer, 114-134, May 2013.

18.    M. Agarwal, D. Pasumarthi, S. Biswas and S. Nandi, "Machine Learning Approach for Detection of Flooding DoS attacks in 802.11 Networks and Attacker Localization", International Journal of Machine Learning and Cybernetics, Volume 7, Issue 6, pp 1035-1051,Impact factor 1.699.

19.    P. Biswal and S. Biswas, "A Polynomial Algorithm for Diagnosability of Fair Discrete Event Systems", Systems Science and Control Engineering, Taylor and Francis, Volume 3, Issue 1, Pages 307-319, 2015 .

20.    P. Biswal and S. Biswas, "A Binary Decision Diagram based Online Testing of Digital VLSI Circuits for Feedback Bridging Faults", Microelectronics Journal, Elsevier, Volume 46, Issue 7, Pages 598-616, 2015, Impact Factor: 1.163.

21.    M. Agarwal, D. Pasumarthi, S. Biswas and S. Nandi, Advanced Stealth Man in the Middle Attack in WPA2 Encrypted Wi-Fi Networks", in the IEEE Communications Letters, Vol. 19, No. 4, pp. 581-584, 2015, Impact Factor 1.988.

22.    P K Biswal, K Mishra, Santosh Biswas and Hemangee Kapoor, A Discrete Event System Approach to Online Testing of Asynchronous Circuits, Journal of VLSI Design, Hindawi. Article ID 651785, 16 pages, 2015,Impact factor 0.54.

23.    Rajesh D, Arnab Sarkar and Santosh Biswas, A Design Fix to Supervisory Control for Fault-tolerant Scheduling of Real-time Multiprocessor Systems with Aperiodic Tasks. International Journal of Control, Taylor & Francis (Vol. 88, No. 11, page 2211-2216), 2015 Impact Factor: 2.208.

24.    F A Barbhuiya, M. Agarwal, S. Purwar, S. Biswas and S. Nandi, "Application of Stochastic Discrete Event System Framework for Detection of Induced Low Rate TCP Attack", ISA Transactions, Elsevier, Vol. 58, pp. 474-492, September 2015, Impact Factor: 3.394.

25.    B. Subba, S. Biswas, S Karmakar, Intrusion Detection in Mobile Ad hoc Network: Bayesian Game Formulation", Engineering Science and Technology: an International Journal., Elsevier, Volume 19, Issue 2, June 2016, Pages 782-799 .

26.    PK Biswal, HP Sambho, S Biswas, "A Discrete Event System approach to On-line Testing of digital circuits with measurement limitation", Engineering Science and Technology, an International Journal, Volume 19, Issue 3, 2016, Pages 1473-1478 .

27.    M. Agarwal, S Purwar, S. Biswas and S. Nandi, "Intrusion Detection System for PS-Poll DoS Attack in 802.11 Networks using Real Time DES", in the IEEE/CAA Journal of Automatica Sinica, IEEE, Volume: 4, Issue: 4, Pages 792-808,2017 Impact Factor: 2.16.

28.    M. Agarwal, S. Biswas and S. Nandi, "Discrete Event System Framework for Fault Diagnosis with Measurement Inconsistency: Case Study of Rogue DHCP Attack, in the IEEE/CAA Journal of Automatica Sinica, IEEE, Volume: PP, Issue: 99, Pages 1-18, 2017 Impact Factor: 2.16.

29.    R. Devaraj, A. Sarkar, S. Biswas, " Comments on Supervisory control for real-time scheduling of periodic and sporadic tasks with resource constraints" IFAC Automatica, Volume 82, Pages 332-334 ,2017, Impact Factor: 5.451

30.    R. Devaraj, A. Sarkar, S. Biswas, "Fault-Tolerant Preemptive Aperiodic RT Scheduling by Supervisory Control of TDES on Multiprocessors, ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 3,Pages 87:1-87:25 ,2017Impact Factor: 1.367.

31.    B. Subba, S. Biswas, S Karmakar, "False Alarm Reduction in Signature based IDS: Game Theory Approach, Journal of Security and Communication Networks, Wiley, Volume 9, Issue 18, 2016, Impact Factor: 1.067.

32.    Rahul Bhattacharya, Subindu Kumar, Santosh Biswas, " Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter ", International Journal of Circuit Theory and Applications, Wiley, Volume 45, Issue 11 , Pages 1701-1741 ,2017 , Impact Factor: 1.571.

33.    Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, "A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks", "Journal of Electronic Testing: Theory and Applications", Volume 33, Issue 2, pp 227-254, April 2017, Springer , Impact Factor 0.647.

34.    Pradeep Kumar Biswal, Santosh Biswas, "On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams", "Microelectronics Journal", Volume 67, pp 88-100, August 2017, Elsevier , Impact Factor: 1.163.

35.    Rahul Bhattacharya, Subindu Kumar, Santosh Biswas, "Fault Diagnosis in Switched-Linear Systems by Emulation of Behavioral Models on FPGA: A case study of current-mode buck converter", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, 2017, Impact Factor: 0.622

36.    Basant Subba, Santosh Biswas, Sushanta Karmakar, "A game theory based multi layered intrusion detection framework for VANET", Future Generation Computer Systems (FGCS), Elsevier Volume 82, 2018, Pages 12-28 , Impact Factor: 3.997.

37.    Amrita Bose Paul, Santosh Biswas, Sukumar Nandi, Sandip Chakraborty, "MATEM: An Unified Framework based on Trust and MCDM for Assuring Security, Reliability and QoS in DTN Routing", Journal of Network and Computer Applications (JNCA), Elsevier , Volume 104, 2018, Pages 1-20,Impact Factor: 3.500 .

38.    Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab Bhattacharya, "Reliability-Aware Test Methodology for Detecting Manufacturing Short-Channel Faults in On-Chip Networks", "IEEE Trans. on VLSI systems", IEEE (accepted),Impact factor 1.698.

39.    Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, "On-line Analysis of Stuck-at Faults in on-Chip Network Interconnects", "Journal of Circuits, Systems, and Computer", World Scientific (Accepted) , Impact factor 0.481.

40.    R. Devaraj, A. Sarkar, S. Biswas, "Supervisory Control Approach and its Symbolic Computation for Power-aware RT Scheduling", IEEE Trans. on Industrial Informatics, IEEE (accepted), Impact factor 6.76.

41.    M. Agarwal, S. Biswas and S. Nandi, "An Efficient Scheme to Detect Evil Twin Rogue Access Point Attack in 802.11 Wi-Fi Networks", International Journal of Wireless Information Networks (IJWI) (accepted), Springer, Impact factor 1.38 .

42.    Basant Subba, Santosh Biswas, Sushanta Karmakar, "A game theory based multi layered intrusion detection framework for wireless sensor networks", International Journal of Wireless Information Networks (IJWI) (accepted), Springer, Impact factor 1.38 .

43.    P.P. Nair A. Sarkar, S. Biswas, "Design of Light Weight Exact DES Diagnosers using Measurement Limitation: Case Study of EFI system", International Journal of Systems Science, Taylor and Francis (accepted), Impact factor 2.285.



Publications (National Journal)   :

1.    S. Biswas, Siddhartha Mukhopadhyay, Amit Patra, D Sarkar, "A Discrete Event System approach for Fault Detection and Diagnosis and On-Line Testing of Digital VLSI Circuits Part1: Theory", Journal of System Science and Engineering, System Society of India, Volume 2015, Article ID 651785, 16 pages,Impact factor 0.915.

2.    S. Biswas, Siddhartha Mukhopadhyay, Amit Patra, D Sarkar, "A Discrete Event System approach for Fault Detection and Diagnosis and On-Line Testing of Digital VLSI Circuits Part2: Case study of Digital VLSI Circuits", Journal of System Science and Engineering, System Society of India, Volume 2015, Article ID 651785, 16 pages,Impact factor 0.915.

2.    Santosh Biswas, "Use of On-line Testing for Design of Reliable VLSI Circuits: A Case study of DCDC Buck Converters", Electrical India Magazine, Vol 49, No 7 July 2009, pp 94-101 (Invited Paper).



Publications and Presentations (Conferences)   :

1.    Vijay Kumar, Santosh Biswas, Siddhartha Mukhopadhyay, "An approach to rapid prototyping for digital circuit and system design -A design case study for IEEE 1149.1 compliance of digital cores", Proc. of 26th NSC 2003, pp 105-109.

2.    Santosh Biswas, Sushanta Mandal, Tapan Pattnayak, "Automatic Test System for Testing VLSI Circuits", Proc. of 27th NSC 2002, IIT Kharagpur, pp 5.1-5.13.

3.    MS Thesis "A Discrete Event Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation": Research Scholar Forum 17th International Conference of VLSI Design 2004, Mumbai, INDIA (presentation)

4.    Santosh Biswas, S.Mukhopadhyay, Amit Patra "Optimization of the theory of FDD for alleviation of State Explosion Problem and development of CAD tools for on-line testing of Digital VLSI Circuits", IEEE IOLTS 2004, Portugal, pp 184.

5.    Santosh Biswas, Siddhartha Mukhopadhyay and Amit Patra "A Discrete Event Approach to On-Line Monitoring of Digital VLSI Circuits", IEEE International Conference on System Man and Cybernetics, October 10-13 2004, Netherlands, pp-1169-1175

6.    Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra "A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: Design and Implementation", VLSI Design & Test Workshops, August 26-28, 2004, Mysore pp. 457-466.

7.    T.Pattnayak, S.Biswas, S.Mukhopadhyay, A.Patra "Built In Self-Test of a Charge Pump Based Phased Lock Loop: A Case Study of High Speed Mixed Signal BIST", IEEE European Test Conference 2004, France.

8.    Projit Nandi, Tapan Pattnayak; Santosh Biswas, Amit Patra, Siddhartha Mukhopadhyay "A New Approach to Analog Scan using Time Delays", VLSI Design & Test Workshops, August 26-28, 2004, Mysore, pp. 549-552.

9.    S. Mandal, S. Biswas, A. K. Sinha, Siddhartha Mukhopadhyay, Amit Patra "A Heuristic Algorithm for Economic Generation Planning" International Conference on Power Systems Challenges to Electric Utilities in the New Millennium November 3 - 5, 2004, Kathmandu, Nepal, pp. 619-624.

10.    Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, "A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool", IEEE Asian Test symposium, 2004, Taiwan, pp. 189-194.

11.    S. Mukhopadhyay, P. Dasgupta, D. Sarkar, S. Sural, P. P. Chakrabarti, S Biswas, B Chatterjee, A. Mandal, S. Mandal, S Pandit, R Paul, S. K. Baranwal, A. Somani, "Towards a Semi-Automated Environment for Design, Verification, Layout and Testing of Analog and Mixed Signal Circuits", Cadence Designers Forum 2004, India.

12.    S.Biswas, D.Sarkar, P.Bhowal, S.Mukhopadhyay, A. Patra, "A new Concept of Fair Diagnosability in Hybrid Dynamical Systems" IEEE INDICON 2004, IIT Kharahpur, India pp. 214-218.

13.    Abu Zar Hashmi, Santosh Biswas, Dipti Ranjan Pal, Siddhartha Mukhopadhyay "A Partition Based Methodology for Simulation Acceleration of Digital VLSI Circuits using FPGAs" IEEE INDICON 2004, IIT Kharagpur, India, pp. 31-34.

14.    S.Biswas, D.Sarkar, S.Mukhopadhyay, "A Hybrid Systems Approach to On-Line Testing of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters, Part1: Theory", NCCDS 2005, IIT Mumbai INDIA.

15.    S Biswas, B Chatterjee, and A Patra, " A Hybrid Systems Approach to On-Line Testing of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters Part 2: A Case Study", NCCDS 2005, IIT Mumbai INDIA.

16.    Preliminary works of PhD thesis "On-Line Testing of Analog Circuits: A Case study of DCDC converters", Research Scholar Forum 18th IEEE International conference on VLSI Design 2005, Kolkata, INDIA (presentation)

17.    C. Karfa, J.S.Reddy, S.Biswas, C.R.Mandal, D.Sarkar, "SAST: an interconnection aware high-level synthesis tool", VLSI Design & Test Symposium, 2005, Banglore, pp. 285-293.

18.    S.Moghe, S Biswas, S Mukhopadhyay, A Patra, D Sarkar "A Hybrid System Approach to Failure Diagnosis of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters", VLSI Design & Test Symposium, 2005, Banglore, pp. 246-255.

19.    S Biswas, P Srikanth, S Mukhopadhyay, A Patra, D Sarkar, "On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models", IEEE Asian Test Symposium. 2005, Kolkata, INDIA, pp. 88-94.

20.    S Biswas, Jintendra K Agrawal, Dipankar Sarkar, Siddhartha Mukhopadhyay and Amit Patra, "Use of On-Line Testing for Design of Reliable VLSI Circuits", International Conference on Reliability and Safety Engineering, IIT Kharagpur, 2005, pp.697-708.

21.    S. Biswas, B Chatterjee, S Mukhopadhyay, A Patra, "A Novel Method for On-Line Testing of Mixed Signal "System On a Chip": A Case study of Base Band Controller, 29th National System Conference, IIT Mumbai, INDIA 2005, pp- 2.1-2.23.

22.    S Biswas, B Maity, S Mukhopadhyay, A Patra, A BIST Approach to On-line Testing of "System on Chip (SoCs)": Theory and Application, IINC 2005, IIT Mumbai, pp 1.1-1.6.

23.    S. Biswas, A Patra, S Mukhopadhyay "Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Bridging Faults and n-Detect Test", proc. IEEE LATW 2006, Argentina, pp- 49-54.

24.    S Biswas, S Mukhopadhyay, A Patra D Sarkar, "Concurrent Testing of Digital Circuits for Advanced Fault Models", IEEE DDECS 2006, Czech Republic, pp. 204-209.

25.    S Biswas, C Karfa, H Kanwar, D Sarkar, A Patra, S Mukhopadhyay, "Fairness of Transitions in Diagnosability Analysis of Hybrid Systems", Proc. American Control Conference, USA, 2006, pp2664-2669.

26.    S Biswas, S Mukhopadhyay, A Patra D Sarkar, "Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Resistive Bridging Fault Model and n-Detect Test", IEEE European Test Symposium 2006, Southampton, UK, pp. 129-134.

27.    S Mondal, V Jaiswal, Santosh Biswas, S Mukhopadhyay, Amit Patra, "Automatic Test Pattern Generation for Board Level Testing of IEEE 1149.1 Compatible Systems", National Seminar on Electronics, Devices and Circuits 2006, BITS Mesra, pp-75-78.

28.    S. Mondal, D. Patra, S. K. Panda, S. Biswas, S. Sural and A. Patra, "Strategy Based Layout Automation of Analog Test Structures", National Seminar on Electronics, Devices and Circuits 2006, BITS Mesra, pp- 79-82.

29.    S Biswas, D Sarkar, S Mukhopadhyay, A Patra, "Diagnosability Analysis of Real Time Hybrid Systems", IEEE ICIT 2006, IIT Mumbai, pp. 104-109.

30.    M Rajaneesh, A Roy, S Biswas, S Mukhopadhyay, A Patra, "an efficient methodology for automatic test pattern generation and testing of digital circuits in mixed signal systems:", International Conference on Reliability and Safety Engineering, IIT Kharagpur, 2006.

31.    M Rajaneesh, R Bhattacharya, S Biswas, S Mukhopadhyay, A Patra "A New approach for testing of digital modules in mixed signal VLSI circuits", IEEE VDAT 2007, pp:196-204.

32.    M Rajaneesh, R Bhattacharya, S Biswas, S Mukhopadhyay, A Patra A New Approach for Test Pattern Generation for Digital Cores in Mixed Signal Circuits IEEE ADCOM 2007, IIT Guwahati, pp. 3-8.

33.    Kumar Garje, Srikanth Pam, Amitava Banerjee, Santosh Biswas, and Siddhartha Mukhopadhyay, "Macromodel based Fault simulation of Opamp using Parameters Estimation, VDAT 2008, pp. 38-48.

34.    S. Biswas, S. Samanta, D. Sarkar, S. Mukhopadhyay, A. Patra, ``Hybrid System Approach to On-Line Testing of Mixed Signal VLSI Circuits: A Case Study of DC-DC Buck Converters", IFAC World Congress-2008, South Korea, pp. 2180-2187.

35.    Kiran Garje, Amitava Banerjee, Pam Srikanth, Santosh Biswas, S. Mukhopadhyay, Anil Kumar, "Macromodel Based Fault Simulation of Linear Circuits using Parameter Estimation", IEEE ICIIS 2008, IIT Kharagpur, pp. 1-6

36.    Neminath Hubballi, Santosh Biswas, Sukumar nandi, "An efficient data structure for storing network intrusion detection dataset" IEEE ANTS 2008, IIT MUMBAI, pp 1-3.

37.    Neminath Hubballi, Santosh Biswas, Sukumar Nandi, "Fuzzy mega cluster based anomaly network intrusion detection", IEEE Network and Service Security 2009, France, pp. 1-5.

38.    Chiranjeevi Yarra, Santosh Biswas and Siddarth Mukhopadhyay, "Synthesis of Analog Inputs for Testing of Digital Modules in Mixed Signal VLSI Circuits", VDAT 2009, pp.

39.    Tarun Kochar, Sukumar Nandi, Santosh Biswas, " A Single chip implementation of AES cipher and Whirlpool hash function", IEEE INDICON 2009, page 1-8

40.    Neminath Hubballi, Santosh Biswas, Sukumar Nandi "Layered higher order n-grams for hardening payload based anomaly intrusion detection", International Conference on Availability, Reliability and Security (ARES 2010), Poland, page 321-326

41.    Rahul Bhattacharya, Amitava Banerjee, Santosh Biswas, Siddhartha Mukhopadhyay "FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits", FPGA 2010, page 284, ACM SIG

42.    A.Khan, K.Misra, S. Biswas, J. Deka, H. Kapoor, "Fair Diagnosability in PN-based DES Models", IEEE international Conference of Control and Automation 2010, Xiamen, China, pp- 2116-2171. (IEEE Press)

43.    Neminath Hubballi, S. Roopa, Ritesh Ratti, F. A. Barbhuiya, Santosh Biswas, Arijit Sur, Sukumar Nandi, Vivek Ramachandran, "An Active Intrusion Detection System for LAN Specific Attacks", International Conference on Information Security and Assurance, 2010, pp-129-142 (LNCS)

44.    Neminath Hubballi, Roopa S, Ritesh Ratti, F Barburiya, Santosh Biswas, Sukumar Nandi, Arijit Sur, Vivek Ramachandran, "A Discrete Event System Approach to Intrusion Detection System for LAN Attacks Presentation format", 18th Mediterranean Conference on Control and Automation, Marrakech, Morocco, IFAC, 2010, pp 695-700.

45.    Bidyut Kr. Patra, Neminath Hubballi, Santosh Biswas, Sukumar Nandi, "Distance Based Fast Hierarchical Clustering Method for Large Datasets", International Conference on Rough Sets and Current Trends in Computing (RSCTC 2010) Poland, 2010, pp 50-59 (LNCS).

46.    Santosh Kumar, Sukumar Nandi and Santosh Biswas, "Peer-to-Peer Network Classification using nu-Maximal Margin Spherical Structured Multiclass Support Vector Machine", in the Second International Conference on Data Engineering and Management, July 2010 (LNCS), (In press).

47.    A. Patro, S. Biswas, D. Goswami, "Use of Reliability Metrics to Compare Bit Torrent and Network Coding", International Conference on Communication, Computers and Devices (ICCCD) 2010, IIT Kharagpur, pp-1-6.

48.    F.A. Barbhuiya, S Roopa, R Ratti, Neminath H, S Biswas, S Nandi, A Sur and V Ramachandra, "An Active Host-based Detection Mechanism for ARP-related Attacks", International Conference on Network & Communications Security (Netcom 2010), Chennai, India, pp- 432-443 (Springer).

49.    Gopal Paul, Santosh Biswas, Chittaranjan Mandal, and Bhargab B. Bhattacharya, "A BDD-based Approach to Design Power-aware On-line Detectors for Digital Circuits", 23rd IEEE International SOC conference 2010, USA, page 343-346.

50.    Neminath Hubballi, Santosh Biswas, Sukumar Nandi, "Sequencegram: n-gram Modeling of System Calls for Program based Anomaly Detection", International Conference on COMmunication Systems and NETworkS (COMSNETS) 2011, Bangalore, India, p-, 1-10 (IEEE)

51.    Santosh Kumar, Sukumar Nandi, Santosh Biswas, "Research and Application of One-Class Small Hypersphere Support Vector Machine for Network", International Conference on COMmunication Systems and NETworkS (COMSNETS) 2011, Bangalore, India, pp, 1-4 (IEEE)

52.    Ferdous Barbhuiya, Santosh Biswas, Neminath Hubballi and Sukumar Nandi, "A Host Based DES Approach for Detecting ARP Spoofing", IEEE Symposium on Computational Intelligence in Cyber Security 2011, Paris, (In press)

53.    F.A. Barbhuiya, N Hubballi, Santosh Biswas and Sukumar Nandi, "Completeness of LAN Attack Detection using Discrete Event Systems", International Conference on Network & Communications Security (Netcom 2011), Chennai, pp 131-139 (Springer)

54.    G. Bansal, N Kumar, F.A. Barbhuiya, antosh Biswas and Sukumar Nandi "Scalable Implementation of Active Detection Mechanism for LAN based Attacks" International Conference on Network & Communications Security (Netcom 2011), Chennai, pp 258-267 (Springer)

55.    Santosh Biswas, "On use of Petri-nets for Diagnosing Nonpermanent Failures", 19th Mediterranean Conference on Control and Automation, Greece, 2011, pp 606-611 (IEEE).

56.    F.A. Barbhuiya, Santosh Biswas and Sukumar Nandi, "An Active DES Framework to Intrusion Detection System for ARP Spoofing", IEEE International Conference on System, Man and Cybernetics 2011, pp 2743-2748, USA, 2011.

57.    Amrita Bose Paul, Upola Gogoi, Shantanu Konwar, Sukumar Nandi, Santosh Biswas, "E-AODV for Wireless Mesh Networks and its Performance Evaluation", Sixth International Conference on Broadband and Wireless Computing, Communication and Applications 2011, Spain 26-33, 2011

58.    F.A. Barbhuiya, Santosh Biswas and Sukumar Nandi, "Detection of Neighbor Solicitation And Advertisement Spoofing in IPv6 Neighbor Discovery Protocol", ACM International Conference on Security of Information and Networks (SIN) 2011, Australia (ACM SIGSAC), pages 111-118, 2011.

59.    A. Rai, F. Barbhuiya, A. Sur, S. Biswas, S. Chakraborty and S. Nandi, "Exploit Detection Techniques for STP using Distributed IDS", the World Congress on information and Communication Technologies, December 12-14, Pages 939-944, 2011.

60.    S. Konwar, A. Bose Paul, S. Nandi and S. Biswas, "MCDM based Trust Model for Secure Routing in Wireless Mesh Networks", the World Congress on information and Communication Technologies, December 12-14, pages 910-915, 2011.

61.    Ferdous Barbhuiya, Vaibhab Gupta, Santosh Biswas and Sukumar Nandi, "Detection and Mitigation of Induced Low rate TCP-targeted Denial of Service attack", IEEE International Conference on Software Security and Reliability (SERE), USA, pp 291-300, 2012.

62.    Ferdous Barbhuiya, Roopa S, Ritesh Ratti, Santosh Biswas, Sukumar Nandi, "An Active Detection Mechanism for Detecting ICMP Based Attacks", IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), pp 51-58, 2012

63.    Gunjan Bansal, Niteesh Kumar, Santosh Biswas, Sukumar Nandi, "Detection of NDP Based Attacks using MLD", ACM International Conference on Security of Information and Networks (SIN), pp 163-167 2012 (ACM SIGSAC).

64.    Santosh Biswas, "Equivalence of Fair Diagnosability and Stochastic Diagnosability of Discrete Event Systems", IEEE Conference on System Man and Cybernetics (IEEE SMC) , UK, Page 378-383, October 2013

65.    Niteesh Kumar, G Bansal, Santosh Biswas and S Nandi, "Host based IDS for NDP related attacks:NS and NA Spoofing", IEEE INDICON 2013, Pages 1-6, Mumbai India

66.    Mayank Agarwal, Santosh Biswas and Sukumar Nandi, "Detection of De-authentication Denial of Service attack in 802.11 networks", IEEE INDICON 2013, Pages 1-6, Mumbai India

67.    Pradeep Biswal and Santosh Biswas, "Diagnosability in Stochastic Petri Net based DES Models", 22nd IEEE Mediterranean Conference on Control and Automation, Page 434 - 439, 2014, Italy

68.    Kamaljeet Chauhan, Piyoosh P and Arnab Sarkar and Santosh Biswas, "A Priori Overload Handling in ERfair Scheduled Embedded Systems: Hybrid Automata Approach", IEEE INDICON 2014, Pages 1-6, Pune, India

69.    Biswajit Bhowmik and J. K Deka and Santosh Biswas, "A Scalable Test Strategy for Detection of Faulty Interswitch Links in 2-D Mesh Networks-on-Chips", IEEE ANTS 2014, pp 1-6.

70.    A. Bose Paul, S Konwar, S Biswas and S Nandi, "M-HRP for Wireless Mesh Networks and its Performance Evaluation", in the Sixth International Conference on Communication Systems and Networks (IEEE/ACM COMSNETS 2014), January 07-09, 2014.

71.    Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, "Crossing Register Transfer Level for VLSI Circuits", International Conference on Industrial Instrumentation and Control (ICIC 2015), May 28-30, 2015, Pune, Maharashtra, India, pp 1608-1613.

72.    Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, "Beyond Test Pattern Generation: Coverage Analysis", International Conference on Industrial Instrumentation and Control (ICIC 2015), May 28-30, 2015, Pune, Maharashtra, India, pp 1620-1625.

73.    B. Bhowmik, S. Biswas, J. K. Deka, "A Packet Address Driven Test Strategy for Stuck-at Faults in Networks-on-Chip Interconnects", 2015 IEEE 23rd Mediterranean Conference on Control and Automation (MED 2015) Spain, pp 176-183

74.    Pradeep Biswal and Santosh Biswas,"Timed Discrete event system approach to online testing of asynchronous circuits," 23rd IEEE Mediterranean Conference on Control and Automation, Pages 341-348, 2015, Torremolinos, Spain. 2015

75.    M Agarwal, S Biswas and S Nandi, "I2-Diagnosability Framework for Detection of Advanced Stealth Man in The Middle Attack in Wi-Fi Networks", in the 23rd Mediterranean Conference on Control and Automation (MED), 2015, pp. 349-356, (IEEE Press)

76.    M Agarwal, S Biswas and S Nandi, "Detection of De-authentication DoS attacks in Wi-Fi Networks: A Machine Learning Approach", in the IEEE SMC , pp 246-251

77.    B. Bhowmik, J. K. Deka, S. Biswas, "Directed Symbolic Execution for VLSI Circuits", 2015 IEEE 28th International Conference on Systems, Man, and Cybernetics (IEEE SMC 2015) Hong Kong, pp 50-55

78.    B. Bhowmik, S. Biswas, J. K. Deka, "An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers", 2015 IEEE 28th International Conference on Systems, Man, and Cybernetics, pp 755-760

79.    B. Bhowmik, J. K. Deka, S. Biswas, "Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects", 2015 ACM 8th Annual India Conference (ACM COMPUTE 2015), pp 19-28

80.    B. Bhowmik, J. K. Deka, S. Biswas, "A Matrix Model for Redefining and Testing NoC Interconnect Shorts", 2015 IEEE 27th Asia Pacific Region Ten Conference (IEEE TENCON 2015) [Winner of Best Paper Award and Young Scientist Award] Macau, pp 1-6

81.    B. Bhowmik, J. K. Deka, S. Biswas, "An Odd-Even Model for Diagnosis of Shorts on NoC Interconnects", 2015 IEEE 12th India International Conference (IEEE INDICON 2015), pp 1-6

82.    Basant Subba, Santosh Biswas, Sushanta Karmakar, "Intrusion Detection Systems using Linear Discriminant Analysis and Logistic Regression", in proceedings of 2015 Annual IEEE India Conference (INDICON) pp 1-6

83.    A B Paul, S Chakraborty, S De, S Nandi and S Biswas, "Adaptive Path Selection for High Throughput Heterogeneous Wireless Mesh Networks", in the IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), December 2015.

84.    Basant Subba, Santosh Biswas, Sushanta Karmakar, "A Neural Network based system for Intrusion Detection and attack classification", in proceedings of 2016 Twenty Second National Conference on Communication (NCC), pp 1-6

85.    B. Bhowmik, S. Biswas, J. K. Deka, "Impact of NoC Interconnect Shorts on Performance Metrics", 22nd National Conference on Communication (NCC-2016), pp 1-6

86.    A Bhandari, M Agarwal, S Biswas and S Nandi, "Intrusion Detection System for Identification of Throughput Degradation Attack on TCP", 22nd National Conference on Communication (NCC-2016), pp 1-6

87.    B. Bhowmik, S. Biswas, J. K. Deka, "An Odd-Even Scheme to Prevent a Packet from Being Corrupted and Dropped in Fault Tolerant NoCs", 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IEEE IOLTS 2016) Catalunya, Spain, pp 195-198

88.    B. Bhowmik, S. Biswas, J. K. Deka, "An On-Line Test Solution for Addressing Interconnect Shorts in on-Chip Networks", 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IEEE IOLTS 2016), Catalunya, Spain, pp. 9-12

89.    B. Bhowmik, J. K. Deka, S. Biswas, B. B. Bhattacharya, "One Poison is Antidote Against Another Poison", 2016 IEEE 29th International Conference on Systems, Man, and Cybernetics (IEEE SMC 2016), pp 004579-004584.

90.    B. Bhowmik, J. K. Deka, S. Biswas, B. B. Bhattacharya, "Detecting and Diagnosing Open Faults in NoC Channels on Activation of Diagonal Nodes", 2016 IEEE 29th International Conference on Systems, Man, and Cybernetics (IEEE SMC 2016), pp 004573-004578.

91.    B. Bhowmik, J. K. Deka, S. Biswas, B. B. Bhattacharya, "On-Line Detection and Diagnosis of Stuck-at Faults in Channels of NoC-Based Systems", 2016 IEEE 29th International Conference on Systems, Man, and Cybernetics (IEEE SMC 2016), pp 004567-004572

92.    B. Bhowmik, J. K. Deka, S. Biswas, B. B. Bhattacharya, "A Topology-Agnostic Test Model for Link Shorts in on-Chip Networks", 2016 IEEE 29th International Conference on Systems, Man, and Cybernetics (IEEE SMC 2016),pp 004561-004566.

93.    B. Bhowmik, J. K. Deka, S. Biswas, "On-Line Testing of Coexistent Stuck-at and Open Faults in NoC Interconnects", 2016 IEEE 28th Region Ten Conference (IEEE TENCON 2016),pp 157 - 162.

94.    B. Bhowmik, J. K. Deka, S. Biswas, "A Concurrent Approach to Detect and Diagnose Shorts in Interconnects of on-Chip Networks", 2016 IEEE 28th Region Ten Conference (IEEE TENCON 2016), pp 2418 - 2423.

95.    B. Bhowmik, J. K. Deka, S. Biswas, "Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in on-Chip Networks", 2016 IEEE 24th International Conference on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (IEEE MASCOTS 2016),pp 394-399.

96.    Basant Subba, Santosh Biswas,Sushanta Karmakar, "Enhancing effectiveness of intrusion detection systems: A hybrid approach", IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016, pp 1-6.

97.    Basant Subba,Santosh Biswas,Sushanta Karmakar, "Enhancing performance of anomaly based intrusion detection systems through dimensionality reduction using principal component analysis", IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016, pp 1-6.

98.    B. Bhowmik, J. K. Deka, S. Biswas, "When Clustering Shows Optimality Towards Analyzing Stuck-at Faults in Channels of on-Chip Networks", The 18th IEEE International Conference on High Performance Computing and Communications (HPCC 2016), Australia, pp 868-875.

99.    B. Bhowmik, J. K. Deka, S. Biswas, "A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in on-Chip Networks", The 18th IEEE International Conference on High Performance Computing and Communications (HPCC 2016) Australia, pp 530-537.

100.    B. Bhowmik, J. K. Deka, S. Biswas, "Charka: A Reliability-Aware Test Scheme for Diagnosis of Channel Shorts Beyond Mesh NoCs", IEEE/ACM DATE 2017, pp 214-219.

101.    R. Devaraj, A. Sarkar, S. Biswas ""Real-time scheduling of non-preemptive sporadic tasks on uniprocessor systems using supervisory control of timed DES" IFAC American Control Conference, 2017, pp 3212-3217

102.    R. Devaraj, A. Sarkar, S. Biswas. Fault-Tolerant Scheduling of Non-preemptive Periodic Tasks using SCT of Timed DES on Uniprocessor Systems. Accepted in: IFAC 2017 World Congress, 2017,pp 9315-9320.

103.    P.P. Nair, R. Devaraj, A. Sen, A. Sarkar, S. Biswas,"DES based Modeling and Fault Diagnosis in Safety-critical Semi-Partitioned Real-time Systems",IFAC World Congress, 2017, pp 5029-5034.

104.    Surajit Das, Chandan Karfa and Santosh Biswas, "MAS Based Accurate Modeling and Progress Verification of NoCs",in 21st International Symposium on VLSI Design and Test (VDAT 2017), July 2017,pp 792-804 .

105.    Mousum Handique, Jatindra Kumar Deka, Santosh Biswas and Kamalika Datta, "Minimal Test Set Generation for Input Stuck-at and Bridging Faults in Reversible Circuits", IEEE TENCON 2017 [Winner of Best Paper Award], pp 234-239.

106.    Basant Subba, Santosh Biswas, Sushata Karmakar, "Host based intrusion detection system using frequency analysis of n-gram terms", IEEE TENCON 2017, pp 2006 - 2011.

107.    R. Devaraj, A. Sarkar, S. Biswas, "Exact Task Completion Time Aware Real-Time Scheduling Based on Supervisory Control Theory of Timed DES", in European Control Conference, 2018 (Accepted).


Message From Director

IIT Bhilai is striving for research-driven undergraduate and postgraduate education. Our objective is to create an education system with multifacet outcomes including research, entrepreneurship, technical leadership, and above all, responsible citizenship. Read More

Newsletter

Subscribe to our Newsletter and stay tuned.